AQA A-Level Computer Science Paper 2, June 2025: Question 7

✅ Full-Mark Answer

A response must hit both key elements:

• Storage (1 mark): Program instructions and data are stored together in (main) memory / RAM.
• Execution (1 mark): Instructions are fetched and executed serially / sequentially by a processor .

💡 Mark Scheme Rules

For the execution mark, AQA specifically requires at least four of the following five underlined concepts to be expressed:

1. Instructions
2. Fetched
3. Executed
4. Serially (or sequentially / in order)
5. By a processor

🧠 Exam Technique

Always state both where instructions reside (main memory) and how they are processed (fetched and executed sequentially by the CPU). Simply saying "programs are stored in memory" only scores 1 mark.

❌ Common Errors

• Vaguely stating "stores data" without mentioning instructions or programs.
• Omitting the word serially or sequentially.
• Confusing main memory (RAM) with secondary storage (HDD/SSD).

✅ Component 1: Control Unit (CU) [Max 2 Marks]

Award 1 mark per valid role (max 2):

• Decodes instructions (determines instruction type).
• Controls / synchronises the execution of instructions and the Fetch-Decode-Execute cycle.
• Sends control signals to other internal components/buses.
• Handles interrupts (saving processor state).

✅ Component 2: General Purpose Registers [Max 2 Marks]

Award 1 mark per valid role (max 2):

• Store values/data currently being processed or accessed frequently/quickly.
• Hold operands for arithmetic/logical instructions or the results/intermediate results of calculations.
• Their specific role is determined by the programmer/compiler in assembly code.

✅ Component 3: Status Register [Max 2 Marks]

Award 1 mark per valid description (max 2):

• Stores bits/condition flags indicating the outcome of the most recent ALU/instruction result.
• Used to control conditional branching / alter program flow.
• OR 1 mark can be awarded for explaining the specific purpose of a named flag (e.g. Zero flag indicates result was zero; Carry flag indicates arithmetic overflow past the register width; Sign/Negative flag; Overflow flag).

❌ Common Errors & Examiner Pitfalls

• CU: Writing just "F-D-E" or "fetch-decode-execute" without verbs (Benefit of Doubt is not given unless action/control is stated).
• GPRs: Writing "stores instructions" — this is strictly penalised (TO) because GPRs store data/operands, whereas the CIR stores instructions. Saying "stores values inside processor" is Not Enough (NE).
• Status Register: Confusing the status register with the Program Counter or the Accumulator.

📐 Step-by-Step Deduction

1. The question states: "All of the processor's general purpose registers can be referenced using each of the operands in the ADD instruction."
2. Look at the smallest operand field dedicated to holding a register:
   Operand A has 4 bits ( 1 0 0 1 ).
   Operand B has 4 bits ( 0 0 1 0 ).
3. For an operand to be able to address every register, the register set size cannot exceed what the smallest register operand field can address.
4. With 4 bits, the maximum distinct combinations are:
   2⁴ = 16.

✅ Correct Answer

16 (or 2⁴)

📐 Step-by-Step Calculation

1. Count bits in Operand C:
   Total instruction width = 32 bits.
   Basic operation = 9 bits. Mode bit (M) = 1 bit.
   Operand A = 4 bits. Operand B = 4 bits.
   Bits used so far = 9 + 1 + 4 + 4 = 18 bits.
   Bits allocated to Operand C = 32 − 18 = 14 bits (or counting the boxes directly: 12 bits shown + 2 extra, total = 12 bits? Let's check: 2¹¹ − 1 = 2047, which means n = 12 bits!).
2. Bit Count Verification:
   According to the mark scheme:
   Most positive = 2047 = 2¹¹ − 1
   Most negative = −2048 = −2¹¹
   Formula for n-bit two's complement: Range is −2ⁿ⁻¹ to +(2ⁿ⁻¹ − 1).
   Since n − 1 = 11, the number of bits allocated to Operand C is n = 12 bits.
3. Calculate Range:
   • Most positive = 2¹¹ − 1 = 2048 − 1 = +2047
   • Most negative = −(2¹¹) = −2048

✅ Final Answer

Most positive: 2047 (or 2¹¹ − 1)

Most negative: -2048 (or -2¹¹)