AQA A-Level Computer Science Paper 2, June 2025: Question 9
7 marks · Medium difficulty · Short Answer
Complete a truth table for an ASCII-decoding logic circuit, deduce the purpose of its outputs, and identify the correct Boolean expression for output Q1.
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Question text
09 Figure 4 shows a logic circuit. The circuit has seven inputs and two outputs.
The inputs B6 to B0 represent the ASCII code of a character, where B6 is the most
significant bit and B0 is the least significant bit. The circuit outputs are Q1 and Q2.
The outputs of six of the gates in the circuit have been labelled U, V, W, X, Y and Z.
Figure 4
Figure 5 shows the ASCII code for printable characters.
Figure 5
ASCII code ASCII code ASCII code ASCII code
Char Binary Char Binary Char Binary Char Binary
SP 0100000 8 0111000 P 1010000 h 1101000
! 0100001 9 0111001 Q 1010001 i 1101001
" 0100010 : 0111010 R 1010010 j 1101010
*#220100011* ; 0111011 S 1010011 k 1101011
$ 0100100 < 0111100 T 1010100 l 1101100
% 0100101 = 0111101 U 1010101 m 1101101
& 0100110 > 0111110 V 1010110 n 1101110
' 0100111 ? 0111111 W 1010111 o 1101111
( 0101000 @ 1000000 X 1011000 p 1110000
) 0101001 A 1000001 Y 1011001 q 1110001
* 0101010 B 1000010 Z 1011010 r 1110010
+ 0101011 C 1000011 [ 1011011 s 1110011
, 0101100 D 1000100 \ 1011100 t 1110100
- 0101101 E 1000101 ] 1011101 u 1110101
. 0101110 F 1000110 ^ 1011110 v 1110110
/ 0101111 G 1000111 _ 1011111 w 1110111
0 0110000 H 1001000 ` 1100000 x 1111000
1 0110001 I 1001001 a 1100001 y 1111001
2 0110010 J 1001010 b 1100010 z 1111010
3 0110011 K 1001011 c 1100011 { 1111011
4 0110100 L 1001100 d 1100100 | 1111100
5 0110101 M 1001101 e 1100101 } 1111101
6 0110110 N 1001110 f 1100110 ~ 1111110
7 0110111 O 1001111 g 1100111
09.1 Complete the truth table below for the input of the ASCII codes of the characters
* @ F W \ and f into the logic circuit shown in Figure 4.
[4 marks]
Inputs Outputs
Char Binary B6 B5 B4 B3 B2 B1 B0 U V W X Y Z Q1 Q2
* 0101010 0 1 0 1 0 1 0
@ 1000000 1 0 0 0 0 0 0
F 1000110 1 0 0 0 1 1 0
W 1010111 1 0 1 0 1 1 1
\ 1011100 1 0 1 1 1 0 0
f 1100110 1 1 0 0 1 241 0
Figure 4 is repeated below to help you answer Questions 09.2 and 09.3 without
having to turn back in the question paper.
*23* Figure 4 (repeated)
09.2 Describe the purpose of the outputs Q1 and Q2 of the circuit in Figure 4.
[2 marks]
Q1
Q2
09 *.243Shade* one lozenge to indicate which of the Boolean equations correctly represents
the output Q1 in Figure 4.
[1 mark]
A Q1 = B6 ⋅ (B���������4⋅B3 + B��� ⋅2 ���������B1⋅B0) ⋅ (B4 + B3 + B2 + B1 + B0) ⋅ ���B5
B Q1 = B6 ⋅ (B��� ⋅4 ���B3 + B��� ⋅2 ��� ⋅B1 ���B0) ⋅ (B4 + B3 + B2 + B1 + B0)
C Q1 = B6 ⋅ (B���������4⋅B3 + B��� ⋅2 ���������B1⋅B0) ⋅ (B4 + B3 + B2 + B1 + B0)
D Q1 = B6 ⋅ ���������B4⋅B3 + B��� ⋅2 ��������� ⋅B1⋅B0 (B4 + B3 + B2 + B1 + B0)
E Q1 = B6 + (B����������� ⋅4+ B3 ���B2 + B����������1+ B0) + (B4 ⋅ B3 ⋅ B2 ⋅ B1 ⋅ B0)
Mark scheme
Show the mark scheme
Total
Qu Pt Marking guidance
marks
09 1 Marks are AO2 (apply) 4
Inputs Outputs
Char Binary B6 B5 B4 B3 B2 B1 B0 U V W X Y Z Q1 Q2
* 0101010 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0
@ 1000000 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0
F 1000110 1 0 0 0 1 1 0 1 0 1 0 1 1 1 1
W 1010111 1 0 1 0 1 1 1 1 0 0 0 1 1 1 1
\ 1011100 1 0 1 1 1 0 0 0 0 1 0 0 1 0 0
f 1100110 1 1 0 0 1 1 0 1 0 1 0 1 1 1 0
1 mark: Columns U and V correct
1 mark: Columns W and X correct
1 mark: Columns Y and Z correct
1 mark: Columns Q1 and Q2 correct
Total
Qu Pt Marking guidance
marks
09 2 Mark are AO2 (analyse) 2
1 mark: Q1 indicates if the character/input is a letter (or not) // 1 indicates a letter
R. 0 indicates letter
R. 1 indicates not letter
1 mark: Q2 indicates if the character/input is a capital/uppercase letter (or not) //
1 indicates a capital/uppercase letter
NE. indicates not a lowercase letter–A-LEVEL COMPUTER SCIENCE – –
R. 0 indicates capital/uppercase letter
R. 1 indicates not capital/uppercase letter
Total
Qu Pt Marking guidance
marks
09 3 Mark is AO2 (analyse) 1
C; Q1 = B6 ⋅ (̅B̅4̅̅ ⋅̅̅ ̅B̅3̅ + ̅B̅2̅ ⋅ ̅B̅1̅̅ ̅⋅̅ B̅̅0̅) ⋅ (B4 + B3 + B2 + B1 + B0)
How to answer it
Logic Circuits & ASCII Character Classification
This question assesses your ability to trace combinational logic circuits, reverse-engineer circuit behaviour using standard bit-representation patterns, and map hardware logic to Boolean expressions.
- Circuit Tracing: Evaluating intermediate gate outputs (NAND, NOT, AND, OR) across multi-bit inputs.
- Character Set Encodings: Understanding standard 7-bit ASCII representations for uppercase letters, lowercase letters, and non-alphabetic symbols.
- Analytical Synthesis: Deducing the high-level functional purpose of circuit outputs (detecting letters vs. uppercase letters).
- Boolean Algebra Mapping: Formulating an unsimplified Boolean expression directly from interconnected logic gates.
Completing the Circuit Truth Table
4 Marks (AO2 - Apply)
📐 Step-by-Step Gate Equations
Write down each intermediate signal from Figure 4 before filling the table:
- U = NAND(B₄, B₃) = ¬(B₄ · B₃)
- V = NOT(B₂) = ¬B₂
- W = NAND(B₁, B₀) = ¬(B₁ · B₀)
- X = AND(V, W) = V · W
- Y = OR(U, X) = U + X
- Z = Cascaded ORs = B₄ + B₃ + B₂ + B₁ + B₀
- Q₁ = B₆ · Y · Z
- Q₂ = Q₁ · ¬B₅
🧠 Exam Technique: Shortcut Patterns
Notice the high-level dependencies to save valuable time:
- Gate Z is 0 only if all inputs B₄ through B₀ are 0. Only the character @ meets this condition.
- Q₁ requires both B₆ = 1 and Z = 1. If either is 0, Q₁ = 0 immediately!
- Q₂ is gated by Q₁: if Q₁ = 0 , then Q₂ is automatically 0 .
✅ Completed Truth Table
| Char | Binary | Inputs | Intermediate Outputs | Final Outputs | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| B₆ | B₅ | B₄ | B₃ | B₂ | B₁ | B₀ | U | V | W | X | Y | Z | Q₁ | Q₂ | ||
| * | 0101010 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| @ | 1000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| F | 1000110 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
| W | 1010111 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| \ | 1011100 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| f | 1100110 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
❌ Common Errors in 09.1
- Misidentifying NAND gates: Treating U or W as simple AND gates. Remember the bubble on the output means invert ( 1 · 1 = 0 , all others produce 1 ).
- Wiring confusion at W: Misreading W's inputs. The inputs come from B₁ and B₀.
- Missing row '@' on Z: For '@', all inputs B₄..B₀ are 0, making Z = 0, which pulls Q₁ down to 0!
• 1 mark: Columns U and V completely correct.
• 1 mark: Columns W and X completely correct.
• 1 mark: Columns Y and Z completely correct.
• 1 mark: Columns Q₁ and Q₂ completely correct.
Describing the Purpose of Outputs Q₁ and Q₂
2 Marks (AO2 - Analyse)
💡 ASCII Character Layout Key Knowledge
Look at the ASCII character patterns in Figure 5:
- Uppercase Letters (A–Z): Binary 1000001 (65) to 1011010 (90). Here, B₆ = 1 and B₅ = 0. The lower 5 bits range from 1 to 26.
- Lowercase Letters (a–z): Binary 1100001 (97) to 1111010 (122). Here, B₆ = 1 and B₅ = 1. The lower 5 bits are identical to uppercase letters!
- Symbols & Punctuation: Character @ is 0, while [ \ ] ^ _ are values 27–31, which are deliberately excluded by gate Y.
✅ Model Answers
Q₁:
Indicates whether the character is an alphabetic letter (or not) // 1 indicates a letter.
Q₂:
Indicates whether the character is an uppercase / capital letter (or not) // 1 indicates an uppercase letter.
❌ Common Misconceptions & Examiner Traps
- "Q₂ indicates not a lowercase letter": NOT ACCEPTED (NE). Non-letters (like numbers, symbols, and punctuation) are also not lowercase letters, but their Q₂ output is 0. Q₂ specifically detects capital letters.
- Inverted logic: Do not say "0 indicates letter". The mark scheme explicitly states REJECT if 0 is described as true.
• 1 mark (AO2) for identifying that Q₁ detects letters (both upper and lower case).
• 1 mark (AO2) for identifying that Q₂ detects uppercase/capital letters.
Identifying the Boolean Equation for Output Q₁
1 Mark (AO2 - Analyse)
Trace the circuit backwards from Q₁ to identify which Boolean expression matches Figure 4.
📐 Circuit Expression Breakdown
- Q₁ is formed by ANDing three main signals:
Q₁ = B₆ · Y · Z - Signal Y expands from gate outputs U and X:
Y = U + X = ¬(B₄ · B₃) + (¬B₂ · ¬(B₁ · B₀)) - Signal Z is the OR sum of B₄ through B₀:
Z = (B₄ + B₃ + B₂ + B₁ + B₀) - Combining everything yields Option C:
Q₁ = B₆ · (¬(B₄ · B₃) + ¬B₂ · ¬(B₁ · B₀)) · (B₄ + B₃ + B₂ + B₁ + B₀)
🧠 Eliminating the Distractors
- Why not A? Option A includes · ¬B₅ at the end. That is the formula for Q₂, not Q₁!
- Why not B? In B, the negation bar spans across the addition symbol (¬(... + ...)) , which represents a NOR gate that is not present in the circuit.
- Why not D or E? Gate connections in D and E incorrectly replace AND operations with OR operations and fail to capture the nested NAND gates.
• 1 mark (AO2) for correctly selecting C.
Topics
4.5 Fundamentals of data representation · 4.6 Fundamentals of computer systems · 4.5.5 Information coding systems · 4.6.4 Logic gates
Question and mark scheme from the AQA A-Level Computer Science examination, Paper 2, June 2025. QuestionVault is an independent revision resource; questions remain the copyright of the awarding body.