AQA A-Level Physics Paper 3 (3BE), June 2025: Question 1

8 marks · Medium difficulty · Short Answer

Complete the circuit diagrams for a digital timer using binary counters and logic gates, construct a logic network from a Boolean expression, and determine the equivalent single gate for a combinational logic circuit.

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Question

Question 01 consists of three parts. Part 01.1 shows a block diagram of a 00 to 59 timer with a 1 Hz generator, two 4-bit binary counters, decoders, and 7-segment displays. Below is an incomplete circuit diagram showing power rails (9 V and 0 V), two 4-bit counter chips with CK, R, and outputs Q0 through Q3, and a push switch S, requiring students to complete the connections and logic gates to count 00 to 59 with a manual reset. Part 01.2 gives the Boolean expression Q = (X.Y) + Z.(X̄.Ȳ) and asks to draw the logic diagram connecting inputs X, Y, Z to output Q. Part 01.3 shows a logic circuit with inputs A and B feeding into a NAND gate and an inverter, whose outputs enter a NOR gate to yield Q, asking which single logic gate (OR, NOR, EOR, AND, NAND) could replace the system.
Question text

01.1 Figure 1 shows a system diagram for a timer designed by a student.

Figure 1

The system displays the numbers from 00 to 59 before resetting.

The timer is designed to count in time intervals of 1 s.

Part of Figure 1 is enclosed within dashed lines.

Figure 2 shows an incomplete circuit diagram for this part of the system.

Figure 2 also includes a switch S that is used to manually reset both counters.

Figure 2

Each counter in Figure 2 advances by 1 when CK receives the rising edge of a pulse.

When R on a counter receives a logic 1, that counter resets.

*02*Complete the circuit diagram in Figure 2 by adding:

• logic gates to select the reset code for each counter

• a link to show how the second counter is triggered from the first counter

• a resistor with switch S to form the manual reset

• logic gates for each of the counters to provide the reset conditions at R.

[5 marks]

01.2 Another student designs a logic system to combine judgements from three people.

When at least two of the three people input logic 1, the system provides an output

of logic 1. Otherwise, the output is logic 0.

The three people are represented by inputs X, Y and Z.

The output Q from this logic system is given by the Boolean expression:

Q = (X • Y) + Z • (X • Y)

Complete Figure 3 to show the combinational logic diagram for this expression.

Use only the logic gates indicated in the expression.

Do not transform the expression.

[2 marks]

Figure 3

01.3 A single logic gate can sometimes be used to replace a more complex logic system.

Figure 4 shows a logic system with inputs A and B and output Q.

Figure 4

Which single logic gate could replace this combinational logic system?

Tick ( ) one box.

[1 mark]

OR

NOR

EOR

AND

NAND

Mark scheme

Show the mark scheme Mark scheme for Question 01: 01.1 awards 5 marks for: LH counter outputs Q1 and Q3 connected to an AND gate; RH counter outputs Q1 and Q2 connected to an AND gate; correct clock triggering link between counters; manual reset switch connected to 9 V with pull-down resistor to 0 V; OR gates combining automatic AND reset outputs with the manual reset line to drive each counter's R input. 01.2 awards 2 marks for correctly drawing an AND gate for (X AND Y) and a NAND gate with inverted inputs connected to an AND gate with Z, all feeding into a final OR gate. 01.3 awards 1 mark for selecting 'AND'.

Question Answers Additional comments/Guidance Mark AO

01.1 Condone lack of connection blobs. 5 2 × AO2

1 mark for correct reset codes for each 3 × AO3

counter (Q1 and Q3 for LH counter, Q1

and Q2 for RH counter)

1 mark for AND gates used with reset

codes

1 mark for correct link between counters

1 mark for correct resistor - switch

arrangement used for manual reset

1 mark for OR gates used to provide all

reset conditions for each counter

– A-LEVEL PHYSICS – –

01.2 Condone no connection blobs on this 2 AO2

occasion.

mp1 for (X AND Y) OR

mp2 for Z AND ((NOT X) NAND (NOT Y))

No penalty after final AND gate in mp2

01.3 AND 1 AO2

Total 8

How to answer it

Digital Logic, Counters & Boolean Systems

📋 What this question tests

This question evaluates your understanding of electronics and digital logic systems, specifically:

  • Cascaded 4-bit binary counters: Resetting at specific modulo counts (mod-10 and mod-6) using logic gates to display 00 to 59.
  • Hardware switching & reset circuits: Using pull-down resistors with switches to provide active-high logic reset pulses.
  • Logic gate synthesis: Implementing compound Boolean expressions directly into combinational logic schematics without simplification.
  • Boolean logic reduction: Simplifying combinational gate networks using Boolean algebra and De Morgan's laws to find equivalent single gates.

Question 01.1

Completing the 00–59 Binary Counter Circuit Diagram (5 Marks)

💡 Key Knowledge

  • Mod-10 (Units / Left counter): Counts 0 to 9, resets as soon as it reaches 10 (decimal 10 = binary 1010₂ ). Reset requires Q₁ = 1 and Q₃ = 1 into a 2-input AND gate.
  • Mod-6 (Tens / Right counter): Counts 0 to 5, resets as soon as it reaches 6 (decimal 6 = binary 0110₂ ). Reset requires Q₁ = 1 and Q₂ = 1 into a 2-input AND gate.
  • Clock Cascading: The clock input ( CK ) of the tens counter must be triggered every time the units counter reaches 10 (connected to the units reset pulse).
  • Active-High Manual Reset (Switch S): Switch connected between +9 V and the junction; a pull-down resistor connected from junction to 0 V. When closed, it delivers 9 V (logic 1); when open, the resistor pulls the line to 0 V (logic 0).
  • Combining Resets: A counter resets if either its automatic code occurs OR manual switch S is pressed → Requires a 2-input OR gate before each counter's reset pin ( R ).

✅ Detailed Circuit Connections

  1. Left Counter Reset (Units): Connect outputs Q₁ and Q₃ to the inputs of a 2-input AND gate.
  2. Right Counter Reset (Tens): Connect outputs Q₁ and Q₂ to the inputs of a second 2-input AND gate.
  3. Inter-counter Link: Connect the output of the Left Counter's AND gate to the CK input of the Right Counter.
  4. Switch & Resistor Network: Connect the top terminal of switch S to the 9 V rail. Connect the bottom terminal of switch S to one terminal of a resistor, and connect the other terminal of the resistor to the 0 V rail.
  5. OR Gates for Reset Pins:
    • Feed one input of OR gate 1 with the LH AND gate output, and the other input from the switch/resistor junction. Output connects to LH Counter R .
    • Feed one input of OR gate 2 with the RH AND gate output, and the other input from the switch/resistor junction. Output connects to RH Counter R .

🧠 Exam Technique & Mark Breakdown

  • Mark 1: Correct binary reset inputs selected ( Q₁ & Q₃ for mod-10; Q₁ & Q₂ for mod-6). Remember the bit weights: Q₀=1, Q₁=2, Q₂=4, Q₃=8 .
  • Mark 2: AND gates used to detect when both reset bits are simultaneously logic 1.
  • Mark 3: Output of the left AND gate wired to trigger the clock input ( CK ) of the right counter.
  • Mark 4: Correct pull-down resistor configuration: Switch between +9 V and junction, resistor between junction and 0 V.
  • Mark 5: OR gates correctly placed between each AND gate output and switch S output to feed reset pin R .

❌ Common Student Errors

  • Floating Inputs: Leaving the switch junction without a resistor to 0 V, causing undefined logic levels when the switch is open.
  • Wrong Reset Numbers: Using 9 ( 1001₂ ) instead of 10 for the units counter, or 5 ( 0101₂ ) instead of 6 for the tens counter. A counter must reach the forbidden state momentarily before resetting.
  • Using AND instead of OR for resets: Combining the switch and auto-reset with an AND gate (which would require pressing the button at the exact microsecond the counter reaches 10 to reset).
AQA Examiner Guidance: Connection blobs (nodes) are condoned if omitted, but lines must clearly meet pins. Ensure gate shapes (curved input on OR, flat input on AND) are distinct to avoid ambiguity.

Question 01.2

Combinational Logic Diagram Implementation (2 Marks)

📐 Expression Breakdown

Target expression: Q = (X · Y) + Z · (X · Y) where the second term is Z · (NOT(X) NAND NOT(Y)) .

Notice the exact form: Q = (X · Y) + Z · (X̅ · Ȳ)

  1. Term 1: X · Y → Inputs X and Y into a 2-input AND gate.
  2. Term 2 Inversions: Inputs X and Y each pass through individual NOT gates (inverters) to form X̄ and Ȳ .
  3. Term 2 NAND: The outputs of the two NOT gates go into a 2-input NAND gate → produces (X̅ · Ȳ) .
  4. Term 2 Product: The output of this NAND gate and input Z feed into a 2-input AND gate → produces Z · (X̅ · Ȳ) .
  5. Sum (OR): Outputs from step 1 and step 4 feed into a 2-input OR gate to give final output Q .

✅ Mark Scheme Requirements

  • Mark 1 (mp1): Correct representation of (X AND Y) fed into an OR gate at the output.
  • Mark 2 (mp2): Input Z AND-ed with the output of a NAND gate whose inputs are NOT X and NOT Y .

🧠 Exam Technique: "Do Not Transform"

  • The rubric states: "Do not transform the expression." Even though X̅ · Ȳ simplifies to X + Y via De Morgan's Laws, you must not substitute it with an OR gate.
  • Draw each operator exactly as written:
    • X̅, Ȳ → NOT gates
    • (···) with bar → NAND gate
    • · → AND gate
    • + → OR gate

Question 01.3

Logic Gate Minimisation (1 Mark)

📐 Step-by-Step Algebraic Reduction

Analyze the gate diagram in Figure 4:

  1. Top gate is a NAND gate with inputs A and B:
    Output₁ = (A · B)
  2. Bottom gate is a NOT gate with input B:
    Output₂ = B̄
  3. Output gate is a NOR gate receiving Output₁ and Output₂ :
    Q = (A · B) + B̄
  4. Apply De Morgan's Law (X + Y) = X̄ · Ȳ :
    Q = (A · B) · B̿
  5. Double negation cancel out ( X̿ = X ):
    Q = (A · B) · B
  6. By Boolean absorption/associativity ( B · B = B ):
    Q = A · (B · B) = A · B

The entire combinational logic circuit simplifies precisely to an AND gate.

✅ Verification via Truth Table

A B (A · B) B̄ NOR Output (Q)
00110
01100
10110
11001

The output column matches that of a standard AND gate (logic 1 only when both A and B are 1).

Correct Box to Tick: [✓] AND

Topics

Optional topics · 3.13 Electronics (A-level only)

Question and mark scheme from the AQA A-Level Physics examination, Paper 3 (3BE), June 2025. QuestionVault is an independent revision resource; questions remain the copyright of the awarding body.