OCR A-Level Computer Science Algorithms and programming (02), June 2025: Question 4
9 marks · Hard difficulty · Extended Response
Discuss the features, execution of four instructions, and justification of pipelining for a processor executing millions of instructions.
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Question text
A processor is being designed to use pipelining and will need to be able to process millions of
instructions.
For each instruction the following stages will be performed:
A the instruction will be fetched from memory
B the instruction will be decoded
C the instruction will be executed
The first four instructions to be processed will be instructions 1, 2, 3 and 4. The design allocates
1-time interval for each of the three stages A, B, C.
Discuss the use of pipelining by this processor.
You should include the following in your answer:
• the features of pipelining
• how pipelining can be used to manage the first four instructions
• a conclusion justifying the use of pipelining in this scenario. [9]
Mark scheme
Show the mark scheme
Question Answer Mark Guidance
4 Mark Band 3 – High level 9 Answers may include, but are not limited to,
(7-9 marks) some of the points below:
The candidate demonstrates a thorough knowledge and
understanding of pipelining; the material is generally accurate AO1: Knowledge
and detailed.
• The division of instructions into a series of
The candidate is able to apply their knowledge and steps
understanding directly and consistently to the context • A different part of each series of steps for
provided. Evidence/examples will be explicitly relevant to the a different instruction can be run by the
explanation. processor at the same time
• An instruction can be fetched whilst
The candidate provides a thorough discussion which is well another is decoded whilst another is
balanced. Evaluative comments are consistently relevant and executed
well-considered.
AO2: Application
There is a well-developed line of reasoning which is clear and
• In the first time interval instruction 1 is
logically structured. The information presented is relevant and
fetched
substantiated.
• 2nd time interval instruction 1 is decoded
Mark Band 2 – Mid level and instruction 2 is fetched
(4-6 marks) • 3rd time interval instruction 1 is executed,
The candidate demonstrates reasonable knowledge and instruction 2 is decoded, instruction 3 is
understanding of pipelining; the material is generally accurate fetched
but at times underdeveloped. • 4th time interval instruction 2 is executed,
instruction 3 is decoded and instruction 4
The candidate is able to apply their knowledge and is fetched
understanding directly to the context provided although one • 5th time interval instruction 3 is executed,
or two opportunities are missed. Evidence/examples are for instruction 4 is decoded
the most part implicitly relevant to the explanation.
The candidate provides a reasonable discussion, the majority
of which is focused. Evaluative comments are, for the most
part appropriate, although one or two opportunities for AO3: Evaluation
development are missed.
• As there are millions of instructions, the
There is a line of reasoning presented with some structure. use of pipelining will make more efficient
The information presented is in the most part relevant and use of processor
supported by some evidence. • …because it reduces/removes latency
• … the CPU is not idle while waiting for
Mark Band 1 – Low Level next instruction
(1-3 marks) • Next instruction is fetched while current
The candidate demonstrates a basic knowledge of pipelining one is decoded/executed
with limited understanding shown; the material is basic and • …more instructions executed per second
contains some inaccuracies. The candidates makes a limited • All parts of the processor can be used at
attempt to apply acquired knowledge and understanding to any instance in time.
the context provided. • Pipelining efficiency reliant on programs
(mostly) executing sequentially …
The candidate provides a limited discussion which is narrow efficiency reduced by jump instructions
in focus. Judgements if made are weak and unsubstantiated. requiring pipeline to be
reset…cost/overhead to be accounted for.
The information is basic and comunicated in an unstructured
way. The information is supported by limited evidence and
the relationship to the evidence may not be clear.
0 marks
No attempt to answer the question or response is not worthy
of credit.
How to answer it
Processor Architecture: Instruction Pipelining
What this question tests
This is a Level of Response (LoR) essay assessing your understanding of CPU microarchitecture. To secure all 9 marks across Band 3 (7–9 marks), you must balance three assessment objectives:
- AO1 (Knowledge): Explaining what pipelining is, how instruction cycles are divided, and concurrent stage usage.
- AO2 (Application): Accurately mapping out the execution of the first four instructions step-by-step across successive time intervals.
- AO3 (Evaluation): Justifying its use when processing millions of instructions, weighing throughput gains against pipeline hazards and stalls (e.g. branch/jump instructions).
Part 1: Features of Pipelining (AO1 Knowledge)
Understanding the mechanics of overlapping instruction phases
💡 Key Knowledge
- Instruction Decomposition: The standard Fetch-Decode-Execute (FDE) cycle is split into distinct, independent sub-tasks or stages ( A: Fetch , B: Decode , C: Execute ).
- Concurrent Execution: Different hardware units execute separate stages for different instructions at the exact same time.
- Parallel Overlap: Whilst instruction n is being executed, instruction n+1 is being decoded, and instruction n+2 is being fetched.
- Hardware Utilization: Keeps all CPU functional units (memory bus, control unit, ALU) active continuously rather than sitting idle.
🧠 Exam Technique: Structuring AO1
Begin your essay by defining the core principle clearly: pipelining does not reduce the time taken to complete an individual instruction; instead, it increases overall instruction throughput by overlapping stages.
Part 2: Managing the First Four Instructions (AO2 Application)
Mapping instruction progression interval-by-interval
📐 Pipeline Progression Trace Table
Assuming 1 time interval per stage ( Stage A = Fetch , Stage B = Decode , Stage C = Execute ):
| Time Interval | Stage A (Fetch) | Stage B (Decode) | Stage C (Execute) | Notes / Pipeline State |
|---|---|---|---|---|
| Interval 1 | Instruction 1 | — | — | Pipeline filling: Only fetch hardware active. |
| Interval 2 | Instruction 2 | Instruction 1 | — | Instruction 1 decoded while Instruction 2 is fetched. |
| Interval 3 | Instruction 3 | Instruction 2 | Instruction 1 | Pipeline is full! Instruction 1 completes execution. |
| Interval 4 | Instruction 4 | Instruction 3 | Instruction 2 | Instruction 2 completes execution. |
| Interval 5 | — | Instruction 4 | Instruction 3 | Instruction 3 completes execution. |
| Interval 6 | — | — | Instruction 4 | Instruction 4 completes execution (pipeline drains). |
✅ Model Answer: Trace Description
In text form, clearly itemise the intervals to guarantee application marks:
- Interval 1: Instruction 1 is fetched from memory.
- Interval 2: Instruction 1 is decoded while Instruction 2 is fetched.
- Interval 3: Instruction 1 is executed, Instruction 2 is decoded, and Instruction 3 is fetched.
- Interval 4: Instruction 2 is executed, Instruction 3 is decoded, and Instruction 4 is fetched.
- Interval 5: Instruction 3 is executed and Instruction 4 is decoded.
- Interval 6: Instruction 4 is executed.
❌ Common Misconceptions to Avoid
- Off-by-one errors: Believing 4 instructions take 4 intervals. Point out that the pipeline requires 3 initial intervals to fill (latency), taking 6 intervals in total to finish all 4 without a continuous stream.
- Assuming identical execution: Forgetting to specify which stage applies to which instruction (e.g. simply stating "1, 2, and 3 are running").
Part 3: Evaluation & Justification (AO3 Evaluation)
Weighing real-world benefits against performance hazards
✅ Key Arguments for Justification
- Massive Throughput Gains: Because the processor handles millions of instructions, the initial 3-cycle fill latency becomes negligible. Once filled, theoretically one instruction finishes every clock interval rather than one every 3 intervals.
- Speedup Factor: Near 3× speed improvement over non-pipelined execution for continuous linear code.
- Resource Efficiency: Prevents ALU and buses from remaining idle during memory retrieval phases.
⚠️ Critical Counter-Arguments (Hazards)
- Branch / Jump Hazards: If an instruction causes a branch (e.g. conditional jump), pre-fetched instructions currently in the decode and fetch stages are invalid.
- Pipeline Flushing: The pipeline must be cleared (flushed) and refilled from the branch target address, causing dead clock cycles (stalls).
- Data Dependencies: An instruction cannot execute if it requires the result of a preceding instruction still in progress.
🧠 The Concluding Judgment (Securing Band 3)
Exemplary conclusion: "In conclusion, pipelining is overwhelmingly justified for this system. When processing millions of instructions, the amortised throughput approaches one completed instruction per clock interval, offering nearly triple the performance. However, because real software contains regular branching and data dependencies, the design must incorporate branch prediction and forwarding techniques to mitigate costly pipeline flushes."
How Marks are Awarded (OCR Assessment Criteria)
Thorough, detailed knowledge of pipelining. Accurately details the 4-instruction lifecycle across intervals. Well-balanced evaluation weighing massive instruction throughput against branch hazards and pipeline flushes, backed by a clear justified conclusion.
Reasonable knowledge of pipelining stages. Shows an attempt to trace instructions across intervals, but may omit intervals or mix up stages. Evaluative points are present (e.g. "it is faster") but superficial or lack discussion of branches/hazards.
Basic recall of Fetch-Decode-Execute. Demonstrates limited or confused application to the four instructions. Little or no relevant evaluation of why it suits millions of instructions.
Topics
1.1 The characteristics of contemporary processors, input, output and storage devices · 1.1.1 Structure and function of the processor
Question and mark scheme from the OCR A-Level Computer Science examination, Algorithms and programming (02), June 2025. QuestionVault is an independent revision resource; questions remain the copyright of the awarding body.