OCR A-Level Computer Science Computer systems (01), June 2025: Question 5

14 marks · Medium difficulty · Short Answer

Complete a truth table and logic circuit for adders, differentiate between half and full adders, and simplify a Karnaugh map expression.

Practise this question

Question

Question 5 contains four parts based on logic circuits and Boolean algebra. Part (a) shows a logic circuit diagram for a half adder consisting of an XOR gate with inputs A and B producing S, and an AND gate with inputs A and B producing C(Out), followed by a 4-row truth table for inputs A and B to be completed. Part (b) asks to describe the difference between a half adder and a full adder circuit. Part (c) provides a partially drawn full adder circuit with inputs A, B, and C(in) and outputs Sum and C(out), requiring completion of the gates and connections. Part (d) displays a 4x4 Karnaugh map for variables AB across the top (00, 01, 11, 10) and CD along the side (00, 01, 11, 10) populated with 0s and 1s, asking to annotate groups and write the simplified expression.
Question text

5 This diagram shows the logic circuit for a half adder.

A

S

B

C (Out)

(a) Complete the truth table for this half adder circuit.

A B S C (Out)

[4]

(b) Describe the difference between a half adder circuit and a full adder circuit.

… [2]

(c) The diagram below shows a partially completed logic circuit for a full adder.

The full adder circuit contains three inputs:

• A – represents the first input

• B – represents the second input

• C(in) – represents the carry bit from the previous stage of the addition.

The full adder circuit contains two outputs:

• Sum – represents the result of adding the three inputs A, B and C(in)

• C(out) – represents the carry that is passed to the next stage of the addition.

Complete the logic circuit to represent a full adder.

A

Sum

B

C(in)

C(out)

18 [4]

(d) This Karnaugh map represents a different logic circuit.

AB

00 01 11 10

00 0 1 1 1

01 0 1 1 0

CD

11 0 0 0 0

10 0 0 1 1

Use this Karnaugh map to find the simplified expression for this circuit.

You should annotate the Karnaugh map to show the groups that you have used to find the

simplified expression.

Write your simplified expression here.

… [4]

Mark scheme

Show the mark scheme Mark scheme for Question 5. For 5(a), the truth table outputs are: S: 0, 1, 1, 0 and C: 0, 0, 0, 1. For 5(b), points given for half adder only adds 2 bits / has no carry in, while full adder can handle a third bit or carry in. For 5(c), points awarded for a new XOR combining the first XOR output and Cin, a new AND joining the first XOR output and Cin, a new OR combining both AND outputs, and correct connections to Sum and C(out). For 5(d), groups are identified as a 2x2 group for (B AND NOT C) and a wrapped 2x2 group across rows 00 and 10 for (A AND NOT D), giving final simplified expression (A AND NOT D) OR (B AND NOT C).

Question Answer Mark Guidance

5 (a) 1 mark for each correct row. 4

A B S C

00 0 0

01 1 0

10 1 0

11 0 1

5 (b) 1 mark for each to max 2: 2

● A half adder can only add 2 single bits // has no Allow: ‘has no carry bit’ for MP1

third bit

H446/01 ● Full adder can handle a 3rd bit/carry inMark Scheme June 2025

Questi Answer Mark Guidance

on

5 (c) 1 mark for each to max 4: 4

● New XOR joining output of first XOR and Cin

● New AND joining output of first XOR and Cin

● New OR joining both AND gates

● Sum and Cout connected, all correct and no additional gates

Solution:

Questi Answer Mark Guidance

on

5 (d) 1 mark for each to max 4: 4

● Correctly identifying group 1 (red group) and correctly identifying group 2 Accept alternative notation:

(blue group) using wrap around AND // ^ // ᐧ

● Identifying (B∧¬C) / B AND NOT C OR // v // +

● Identifying (A∧¬D) / A AND NOT D NOT // ¬ // ¯¯

● Joining all expressions with an OR // v // +

DNA incorrect ¬ shape

Solution: (A∧¬D) ∨ (B∧¬C)

Allow either order e.g.:

B^¬C // ¬C^B

How to answer it

Binary Logic: Adders & Karnaugh Maps

What this question tests

This multi-part question tests your understanding of fundamental binary arithmetic hardware and Boolean logic optimisation:

  • Half Adder logic: Deriving sum and carry outputs using XOR and AND logic.
  • Structural distinctions: Explaining why half adders cannot chain multi-bit arithmetic while full adders can.
  • Circuit composition: Constructing a full adder using two half adders and an OR gate.
  • Karnaugh Map simplification: Identifying adjacent groupings of 1s (including wrap-around cells) to derive minimal Boolean expressions.
Part (a) • 4 Marks

Half Adder Truth Table

Complete the truth table for the half adder circuit

✅ Completed Table

A B S (Sum) C (Carry Out)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

1 mark per fully correct row.

💡 Underlying Logic

  • Sum (S): Implemented via an XOR gate ( A ⊕ B ). Outputs 1 if exactly one input is 1 .
  • Carry (C): Implemented via an AND gate ( A ∧ B ). Outputs 1 only when both inputs are 1 (since 1 + 1 = 10₂).
Examiner Insight: This is a standard recall exercise. Be cautious on row 4 ( 1, 1 ): students in a rush sometimes write S = 1, C = 1 or invert the columns.
Part (b) • 2 Marks

Difference Between Half and Full Adders

Describe the operational difference between the two circuits

✅ Model Answer

  • Half Adder: Can only add two single bits (it has no carry-in input / cannot handle a third bit). [1 mark]
  • Full Adder: Can add three bits simultaneously, accommodating a carry-in ( Cin ) from a previous addition stage. [1 mark]

❌ Common Errors

  • Vaguely stating "a full adder is twice as big" or "a full adder is faster" without referencing the inputs.
  • Claiming a half adder has no carry output. A half adder does produce a carry ( Cout ); it simply cannot accept a carry input ( Cin ).

🧠 Exam Technique

Whenever an exam question asks for a difference, ensure you mention both components explicitly or use a comparative conjunction (e.g. "whereas"). Do not just define one and leave the examiner to infer the other.

Part (c) • 4 Marks

Constructing a Full Adder Circuit

Complete the logic circuit diagram using gates and connections

✅ Required Circuit Structure (Step-by-Step Drawing)

A full adder is constructed by cascading two half adders and combining their carry outputs with an OR gate:

  1. Second XOR Gate: Connect the output of the first XOR ( A ⊕ B ) and the Cin line to the inputs of a new XOR gate. The output of this gate connects to Sum.
  2. Second AND Gate: Connect the output of the first XOR ( A ⊕ B ) and the Cin line to the inputs of a new AND gate.
  3. Final OR Gate: Route the outputs from both AND gates (the provided lower AND gate and your newly added AND gate) into the inputs of an OR gate. Connect the OR gate's output to C(out).
  4. Ensure all lines are properly linked without floating wires or redundant gates.

🧠 Mark Scheme Breakdown

  • Mark 1: New XOR joining output of first XOR and Cin .
  • Mark 2: New AND joining output of first XOR and Cin .
  • Mark 3: New OR joining outputs of both AND gates.
  • Mark 4: Outputs cleanly wired to Sum and C(out) with zero extra/erroneous gates.

❌ Common Drawing Traps

  • Confusing the gate symbols: Drawing an OR gate instead of an XOR gate for the second sum stage.
  • Incorrect carry combination: Combining the carry outputs with an AND gate instead of an OR gate (a carry is generated if either half adder carries).
Part (d) • 4 Marks

Karnaugh Map (K-Map) Simplification

Annotate groupings and write the minimal Boolean expression

📐 Step 1: Map Layout & Group Identification

The 4-variable map has variables AB across columns and CD down rows:

AB
00 01 11 10
CD 00 0 1 1 1
01 0 1 1 0
11 0 0 0 0
10 0 0 1 1
Group 1 (Red 2×2 Block): Cells at AB ∈ {01, 11}, CD ∈ {00, 01}
Group 2 (Blue 2×2 Wrap-Around): Cells at AB ∈ {11, 10}, CD ∈ {00, 10} (top and bottom edges wrap around!)
Overlap: Cell at AB = 11, CD = 00 belongs to both groups.

📐 Step 2: Extract Minimal Terms

  1. Analyse Group 1 (Red Block):
    • A changes ( 0 → 1 ), B remains 1
    • C remains 0 (so ¬C ), D changes ( 0 → 1 )
    • Term: B ∧ ¬C [1 mark]
  2. Analyse Group 2 (Blue Wrap-Around Block):
    • A remains 1, B changes ( 1 → 0 )
    • C changes ( 0 → 1 ), D remains 0 (so ¬D )
    • Term: A ∧ ¬D [1 mark]

✅ Final Simplified Expression

(B ∧ ¬C) ∨ (A ∧ ¬D)

Equivalent acceptable notations:
• Boolean algebra: B¬C + A¬D
• Text syntax: (B AND NOT C) OR (A AND NOT D)

Marking Breakdown:
• 1 mark: Both groups correctly identified on map.
• 1 mark: Deriving B ∧ ¬C .
• 1 mark: Deriving A ∧ ¬D .
• 1 mark: Joining both terms with OR / ∨ / + .

❌ Common Pitfalls

  • Missing edge wrap-around: Many students miss that the top row ( CD = 00 ) and bottom row ( CD = 10 ) are adjacent, creating smaller pairs instead of a single group of 4. Always look for powers of 2 (1, 2, 4, 8) to achieve maximal simplification.
  • Incorrect NOT syntax: OCR requires unambiguous negation symbols such as standard overbars, ¬ , or the written word NOT . Do not invent ambiguous shorthand.

Topics

1.4 Data types, data structures and algorithms · 1.4.3 Boolean Algebra

Question and mark scheme from the OCR A-Level Computer Science examination, Computer systems (01), June 2025. QuestionVault is an independent revision resource; questions remain the copyright of the awarding body.