AQA A-Level Computer Science AS Paper 2, June 2025: Question 7
8 marks · Medium difficulty · Short Answer
Identify an XOR logic gate, determine the type of parity computed by an XOR circuit, and explain how parity bits are used to detect transmission errors.
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Question text
07 Figure 3 shows a logic circuit that can be used to compute a parity bit for a 4-bit
message. In Figure 3 the message 1001 is shown as the input message and the
circuit outputs 0 as the resulting parity bit.
Figure 3
07.1 The logic circuit in Figure 3 uses three logic gates, all of the same type.
State the name of the type of logic gate used in Figure 3 and explain the operation of
this type of logic gate.
[2 marks]
Name
Operation
07.2 State the type of parity that is computed by the logic circuit in Figure 3 and give a
reason for your answer.
[2 marks]
Type of parity
Reason
07.3 Alice wants to send a 4-bit message to Bob but is worried about errors. Alice decides
*10to use a parity bit to allow some error checking.*
Describe how Alice can send the message using a parity bit to allow for error
detection and how Bob can determine if an error has occurred.
As part of your answer you must state when Alice and Bob can make use of a copy of
the logic circuit in Figure 3.
[3 marks]
07.4 Describe one limitation of using a parity bit for error detection.
[1 mark]
Mark scheme
Show the mark scheme
Qu Pt Marking Guidance Marks
07 1 1 mark is for AO1 (knowledge) and 1 mark is for AO1 (understanding) 2
1 mark for AO1 (knowledge):
XOR // X-OR // EXOR // EX-OR // Exclusive OR;
1 mark for AO1 (understanding):
XOR gate produces a 1 on its output when its inputs are different // XOR gate
produces a 1 on its output when there is a 1 on one input and a 0 on the other
input;
Qu Pt Marking Guidance Marks
07 2 Marks are for AO2 (application) 2
Even (parity);
The circuit outputs a 0 in cases where the number of 1s in the input is even (and
outputs a 1 in cases where the number of 1s in the input is odd);
Qu Pt Marking Guidance Marks
07 3 Marks are for AO1 (understanding) 3
Alice uses her (copy of the) logic circuit with the 4-bit message as input to produce
the parity bit;
The parity bit is appended/prepended to the 4-bit message for transmission (of a
5-bit message) across a communication channel;
Bob can detect (single bit) errors by separating out the message received and
comparing the parity bit received against the result of feeding the 4-bit message
into his (copy of the) logic circuit; – – –
Qu Pt Marking Guidance Marks
07 4 Mark is for AO1 (understanding) 1
Parity bits can miss errors when an even number of bits are changed;
Parity bits cannot determine the position of errors (so an entire message must be
resent when an error is detected);
A. Party bits cannot correct errors
Max 1
How to answer it
Parity Bit Generation & Error Detection Circuits
This question assesses your understanding of fundamental data transmission and hardware logic concepts:
- Logic Gate Identification & Truth Tables: Recognising XOR gates and describing their Boolean behaviour.
- Parity Logic: Deducing whether a parity generation circuit implements even or odd parity based on circuit tracing.
- Transmission Protocols: Explaining end-to-end sender/receiver validation procedures using parity bits.
- Evaluation: Identifying critical weaknesses in single-bit error detection schemes.
Identifying & Explaining the Logic Gate
AO1 (Knowledge & Understanding)
✅ Mark Scheme Model Answer
Name: XOR (also accept: X-OR, EXOR, EX-OR, Exclusive OR)
Operation: An XOR gate produces an output of 1 when its inputs are different (i.e. one input is 1 and the other is 0 ), and outputs 0 when both inputs are identical.
[1 mark] for accurate operation description.
💡 Key Knowledge: XOR Truth Table
| Input A | Input B | Output (A ⊕ B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Notice that an XOR gate effectively performs modulo-2 addition: it outputs 1 if the count of 1 s is odd.
❌ Common Errors
- Confusing XOR with standard OR (e.g. answering "outputs 1 if at least one input is 1").
- Writing "Exclusive NOR" (XNOR) — make sure to note the absence of an inversion bubble at the output!
🧠 Exam Technique
Always state both conditions for full clarity: when the gate outputs 1 (inputs are different) and/or when it outputs 0 (inputs are the same).
Deducing Parity Scheme Type
AO2 (Application)
✅ Mark Scheme Model Answer
Type of parity: Even (parity)
Reason: The circuit outputs a 0 when the number of 1 s in the input message is even (or outputs a 1 when the number of 1 s is odd), ensuring the total count of 1 s across all 5 bits remains even.
[1 mark] for valid reasoning linking input bit count to output.
📐 Circuit Tracing Steps
- Input message is 1001 (contains two 1 s — an even number).
- Top XOR: inputs 1 and 0 → Output = 1
- Bottom XOR: inputs 0 and 1 → Output = 1
- Final XOR: inputs 1 and 1 → Parity Output = 0
- Total 1 s sent = 2 (data) + 0 (parity) = 2 (Even).
❌ Common Errors
Assuming that because the output is 0 , it must mean "Odd Parity" or represents an error. Parity is defined by the total number of 1s in the transmitted codeword.
🧠 Exam Technique
Test a quick mental edge-case: If the input were 1110 (three 1s, odd), the outputs would be 0 and 1 → final XOR = 1 . Total 1s = 3 + 1 = 4 (Even). Hence, this is definitively an even parity generator.
Transmission & Verification Protocol
AO1 (Understanding)
✅ Mark Scheme Model Answer
- Alice (Sender): Feeds her 4-bit message into her copy of the logic circuit to generate the parity bit.
- Transmission: Appends (or prepends) the generated parity bit to the 4-bit message to form a 5-bit block and transmits it across the communication channel.
- Bob (Receiver): Separates the received parity bit from the 4-bit message, feeds the 4-bit message into his copy of the logic circuit, and compares the circuit's output against the received parity bit to detect single-bit errors.
[1 mark] Parity bit is attached to create a 5-bit message for transmission.
[1 mark] Bob separates message, recalculates parity using his circuit, and compares.
🧠 Top-Level Response Structure
Notice the explicit command in the question: "state when Alice and Bob can make use of a copy of the logic circuit".
To secure all 3 marks, structure your answer chronologically:
- Step 1: Alice's computation (circuit used)
- Step 2: Message packaging & sending
- Step 3: Bob's verification (circuit used + comparison made)
❌ Why Students Lost Marks
- Forgetting to explain how Bob uses the circuit (many candidates only explained Bob counting the 1s manually instead of using his copy of the circuit).
- Failing to mention that the parity bit is combined with the message during transmission (creating a 5-bit packet).
Limitation of Parity Checking
AO1 (Understanding)
✅ Mark Scheme Acceptable Answers (Any One)
- Cannot detect errors if an even number of bits change (e.g. a 2-bit error where two bits flip, cancelling each other out).
- Cannot determine the position of the error (meaning bits cannot be corrected; the entire message must be resent).
- Parity bits cannot correct errors (error detection only, not error correction).
❌ Common Errors
Vague statements such as "it doesn't work for large data" or "it is slow" score 0. You must reference the specific vulnerability to an even number of transposed/corrupted bits or the inability to locate/correct the corrupted bit.
Topics
4.6 Fundamentals of computer systems · 4.9 Fundamentals of communication and networking · 4.6.4 Logic gates · 4.9.1 Communication
Question and mark scheme from the AQA A-Level Computer Science examination, AS Paper 2, June 2025. QuestionVault is an independent revision resource; questions remain the copyright of the awarding body.