AQA A-Level Computer Science AS Paper 2, June 2025: Question 9

5 marks · Medium difficulty · Short Answer

Describe the roles of the MAR and MBR during the fetch stage, and describe what happens during the decode stage of the Fetch-Execute cycle.

Practise this question

Question

Question 09 consists of two parts. Part 09.1 asks students to 'Describe the roles of the memory address register (MAR) and memory buffer register (MBR) in the fetch stage of the Fetch-Execute cycle' for 2 marks, providing designated writing lines for MAR and MBR. Part 09.2 asks students to 'Describe what happens during the decode stage of the Fetch-Execute cycle, including the role of any dedicated registers' for 3 marks, followed by several answer lines.
Question text

09.1 Describe the roles of the memory address register (MAR) and memory buffer register

(MBR) in the fetch stage of the Fetch-Execute cycle.

[2 marks]

MAR

MBR

09.2 Describe what happens during the decode stage of the Fetch-Execute cycle,

including the role of any dedicated registers.

[3 marks]

Mark scheme

Show the mark scheme Mark scheme table for question 09. For part 09.1 (2 marks), MAR: contains address of the instruction/memory location to be fetched; MBR: stores the fetched instruction or value stored at the memory address indicated by MAR. For part 09.2 (3 marks), points include: Current Instruction Register (CIR) stores the instruction currently being decoded/executed; instruction is split into opcode and operand; Control Unit decodes the instruction or determines the type of instruction to carry out.

Qu Pt Marking Guidance Marks

09 1 Marks are for AO1 (understanding) 2

Memory address register (MAR):

(MAR) contains address of the (memory location containing the) instruction to be

fetched;

Memory buffer register (MBR):

The fetched instruction is stored in the MBR // The value stored at the memory

address (indicated by the MAR) is stored in the MBR;

TO. References to storing into RAM/main memory

Qu Pt Marking Guidance Marks

09 2 Marks are for AO1 (understanding) 3

Current instruction register (CIR) stores the instruction currently being

decoded/executed // decode instruction held by CIR;

Instruction is split into opcode and operand;

Control unit decodes the instruction // control unit determines the type of instruction

to carry out;

Qu Pt Marking Guidance Marks

How to answer it

The Fetch-Decode-Execute Cycle & Dedicated Registers

WHAT THIS QUESTION TESTS

This question assesses your deep understanding of processor architecture (AO1 knowledge), specifically:

  • The precise role of dedicated CPU registers ( MAR , MBR , and CIR ).
  • The exact sequence of events occurring during the fetch stage across the system buses.
  • What happens during the decode stage, including the roles of the Control Unit (CU) and instruction components (opcode and operand).
QUESTION 09.1 • 2 MARKS

Roles of MAR and MBR in the Fetch Stage

Describe the roles of the memory address register (MAR) and memory buffer register (MBR) in the fetch stage of the Fetch-Execute cycle.

✅ Mark Scheme Answers

Memory Address Register (MAR):

  • Holds / contains the address of the (memory location containing the) instruction to be fetched. [1 mark]

Memory Buffer Register (MBR):

  • Stores the instruction fetched from memory (or holds the value located at the memory address specified by the MAR). [1 mark]

💡 Key Knowledge

  • MAR: Connected to the Address Bus (unidirectional from CPU to memory). It exclusively holds memory locations/addresses, never instructions themselves.
  • MBR (also known as MDR): Connected to the Data Bus (bidirectional). It acts as a holding bay for anything read from or about to be written to memory.
  • In the fetch stage, the address flows: PC → MAR → Address Bus → Main Memory .
  • The instruction flows: Main Memory → Data Bus → MBR .

🧠 Exam Technique

  • Be stage-specific: The question specifies the fetch stage. While MBR can hold data being written out to memory during execution, during the fetch stage it specifically receives an instruction from memory.
  • Always state what is held: MAR holds an address; MBR holds an instruction/data value.

❌ Common Errors & Misconceptions

  • Talking about execution writes: Stating that MBR stores something into RAM during this stage. The mark scheme explicitly notes: TO (Talk Out) - References to storing into RAM/main memory .
  • Confusing MAR and MBR contents: Writing that MAR holds the instruction itself, or that MBR holds an address.
  • Omitting the word "address": Saying "MAR holds where to go" is too vague for A-Level standard.
Mark Breakdown: 1 mark for stating that MAR contains the memory address of the instruction to be fetched; 1 mark for stating that MBR stores the fetched instruction / contents read from that address.
QUESTION 09.2 • 3 MARKS

The Decode Stage of the Fetch-Execute Cycle

Describe what happens during the decode stage of the Fetch-Execute cycle, including the role of any dedicated registers.

✅ Mark Scheme Answers (Any 3)

  • CIR dedicated register: The Current Instruction Register (CIR) stores the instruction currently being decoded/executed (or instruction held in CIR is decoded). [1 mark]
  • Instruction split: The instruction is split into opcode and operand. [1 mark]
  • Control Unit role: The Control Unit (CU) decodes the instruction (or determines the type of instruction to carry out / what operation to perform). [1 mark]

💡 Key Knowledge

  • Transfer to CIR: At the very start of the decode stage, the instruction moves from MBR → CIR .
  • Opcode: Defines what operation to perform (e.g. ADD, SUB, LDR) and the addressing mode used.
  • Operand: Holds the data to be operated on or the address of the data.
  • Control Unit: Contains the instruction decoder circuitry. It translates the opcode into precise internal control signals sent via the control bus.

🧠 Exam Technique

  • Address the full prompt: The question specifically asked for "including the role of any dedicated registers". If you do not name and explain the CIR, you automatically forfeit a straightforward mark.
  • Use standard assembly terms: Always use the formal terms opcode and operand when explaining how an instruction is unpacked.

❌ Common Errors & Misconceptions

  • Thinking the ALU decodes: The ALU executes mathematical and logical operations; it is the Control Unit (CU) that decodes instructions.
  • Vague descriptions: Describing that "the CPU works out what to do" without naming the Control Unit or splitting the instruction into opcode and operand.
  • Confusing decode with execute: Describing the calculation or the storing of results, which belongs strictly to the execute stage.
Mark Breakdown: Max 3 marks awarded for AO1: 1 mark for identifying CIR holds the instruction; 1 mark for splitting instruction into opcode and operand; 1 mark for Control Unit decoding/interpreting the instruction.

Topics

4.7 Fundamentals of computer organisation and architecture · 4.7.3 Structure and role of the processor and its components

Question and mark scheme from the AQA A-Level Computer Science examination, AS Paper 2, June 2025. QuestionVault is an independent revision resource; questions remain the copyright of the awarding body.